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74ALVCF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26 Series Resistors in Outputs
September 2001 Revised October 2001
74ALVCF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26 Series Resistors in Outputs
General Description
The 74ALVCF162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The 74ALVCF162835 is designed with 26 series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVCF162835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVCF162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
I Compatible with PC133 DIMM module specifications I 1.65V-3.6V VCC specifications provided I 3.6V tolerant outputs I 26 series resistors in outputs I tPD (CLK to O n) 3.7 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 7.4 ns max for 1.65V to 1.95V VCC I Power-down high impedance outputs I Latchup conforms to JEDEC JED78 I ESD performance: Human body model > 2000V Machine model >200V
Ordering Code:
Order Number 74ALVCF162835T Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2001 Fairchild Semiconductor Corporation
DS500668
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74ALVCF162835
Connection Diagram
Pin Descriptions
Pin Names OE LE CLK I1 - I18 O1 - O18 Description Output Enable Input (Active LOW) Latch Enable Input Clock Input Data Inputs 3-STATE Outputs
Truth Table
Inputs OE H L L L L L L LE X H H L L L L CLK X X X In X L H L H X X Outputs On Z L H L H O0 (Note 1) O0 (Note 2)

H L
H = Logic HIGH L = Logic LOW X = Don't Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition Note 1: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 2: Output level before the indicated steady-state input conditions were established.
Logic Diagram
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74ALVCF162835
Absolute Maximum Ratings(Note 3)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 4) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to 4.6V -0.5V to VCC +0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 5)
Power Supply Operating Input Voltage Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
-40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOH = -12 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA IOH High Level Output Current 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 1.65 2.3 2.7 3.0 IOL Low Level Output Current 1.65 2.3 2.7 3.0 II IOZ IOFF ICC ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V, V I = VIH or VIL 0V (VI, VO) 3.6V VI = V CC or GND, IO = 0 VIH = VCC - 0.6V 1.65 - 3.6 1.65 - 3.6 0 3.6 2.7 - 3.6 VCC - 0.2 1.2 1.9 1.7 2.4 2 2 0.2 0.45 0.4 0.55 0.55 0.6 0.8 -2 -6 -8 -12 2 6 8 12 5.0 10 10 40 750 A A mA A A mA mA V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units
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74ALVCF162835
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V 0.3V Min fMAX tPHL, tPLH Maximum Clock Frequency Propagation Delay 1.1 Bus-to-Bus tPHL, tPLH Propagation Delay 1.5 Clock to Bus tPHL, tPLH Propagation Delay 1.1 LE to Bus tPZL, tPZH tPLZ, tPHZ tS tH tW Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width 1.1 1.1 1.5 0.7 1.5 4.8 4.7 1.3 1.3 1.5 0.7 1.5 6.4 5.2 0.8 0.8 1.5 0.7 1.5 5.9 4.7 1.5 1.5 2.5 1.0 4.0 9.8 7.9 ns ns ns ns ns 4.2 1.3 5.2 0.8 4.7 1.5 8.5 ns 3.7 2.0 4.6 1.5 4.1 2.0 7.4 ns 3.6 1.3 4.5 0.8 4.0 1.5 7.2 ns 250 Max VCC = 2.7V Min 200 Max CL = 30 pF VCC = 2.5 0.2V Min 200 Max VCC = 1.8V 0.15V Min 100 Max MHz Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 0 pF TA = +25C VCC 3.3 3.3 3.3 2.5 Typical 3.5 5.5 13 13 pF pF pF Units
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74ALVCF162835
IOUT - VOUT Characteristics
IOH versus VOH
FIGURE 1. Characteristics for Output - Pull Up Drive
IOL versus VOL
FIGURE 2. Characteristics for Output - Pull Down Driver
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74ALVCF162835
AC Loading and Waveforms
Table 1: Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 3. AC Test Circuit Table 2: Variable Matrix ( Input Charactertistics: f = 1MHz; tr=tf=2ns; Z0= 50 ) Symbol Vmi Vmo VX VY VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 4. Waveform for Inverting and Non-inverting Functions
FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
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74ALVCF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26 Series Resistors in Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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